Conformity Magazine

See this article in our Digital Edition
Download a pdf of this article (right click to save the pdf)

Most of us designing boards today face four types of signal integrity issues:

EMI
Crosstalk
Distortion caused by signal reflections
Power system “bounce” and instabilities

All of these issues can present difficult problems to deal with, but many designers seem to find EMI the most difficult because it seems so mysterious. First, it deals with signals induced "out there someplace" by signals that we assume are only within our system. Then the cause (we are told) is usually something called "common-mode" signals. But we don't (usually) design common-mode signals in our systems; we design differential mode signals in our systems. For those with limited experience, it all sounds very complicated and mysterious, indeed.

Well, the truth is that designing PC boards for low EMI emissions in high-speed systems is easy! And having captured your attention with that statement, here are the two primary rules you need to keep in mind to accomplish this:

Make sure every high-speed trace is referenced to an adjacent, continuous power system plane; and,
Structure your board stackup so that there are power/ground plane pairs (providing planar capacitive coupling) for all critical power system voltages.¹

Note the clear requirement for planes. In a high-speed (read fast rise time) environment, planes are very important for many reasons, including provision for controlled impedance traces, control over cross talk, and fast rise time decoupling. It is also very difficult to control EMI without the use of planes. Virtually every high-speed board we have ever designed for any of our customers has included power system planes in its stackup.

Signals on PC boards fall into two broad categories. They are conventionally (and not necessarily accurately) referred to as differential mode (not to be confused with differential traces) and common mode signals. Each of these signal types can be a source of EMI radiation. The distinction between them can be confusing.

Differential mode is the mode we are usually familiar with. That is, a signal travels down a well defined path and returns, in the opposite direction, on another well defined path.² Since the signal and its return flow in opposite directions, the term “differential” is used. Following this logic, “common mode” then refers to the case where the signal flows in the same direction on both the trace and the return.

Since, according to Kirchoff’s Laws, all signals must flow in closed loops, this explanation starts to become troublesome when you really start to think about it. If common mode currents flow in the same direction, how do they return to their source? And then there is the confusion cased by the term “differential mode” in this context, and differential mode in the context of differential signaling and differential traces.

So let’s define “common” and “differential” modes slightly differently. Let’s first use the term “differential mode” (in the context of a single-ended trace) to mean the current flowing where we expect it to flow based on the schematic and the layout. If we have used reference planes in our designs, then most of us have learned that the differential mode (high-speed) signals travel down the trace and return on the plane directly under the trace.

We will now define common mode currents as those that are flowing anywhere else!³

This raises several obvious questions. (1) How can this happen? (2) Even if it happens, what’s the problem? (3) What’s the relationship between this definition and the normal one generally used (above)? (4) What, if anything, can be done about it?

Common Mode Radiation
How Can This Happen?
Figure 1 illustrates one example of differential and common mode currents based on our definition. A signal travels down the trace and returns on the ground plane directly underneath the trace. This is the differential mode signal current, Id. Another part of the signal travels down the trace and returns through a completely different unintended path. This is called the common mode signal current, Ic.

Figure 1: Differential and Common Mode Currents

This can happen for several possible reasons. One is that the ground plane is not a perfect conductor. There is some inductance (admittedly small) associated with it. So there can be a voltage divider action involved where the current splits along the intended path (Id) and some other path(s) (Ic).

Or, perhaps there is a wire, stub, or cable shield (for example a coax cable) attached to the trace. Very fast rise time transients may travel along such paths and radiate to other traces or surfaces. The characteristic impedance of a wire in space is generally known to be on the order of 370 Ohms, which means the impedance along another unintended path could be in this range.

If the impedance along the plane is a fraction of an Ohm and a radiated signal is on the order of 370 Ohms, the amount of current flowing in the alternative path would only be a tiny fraction of the primary (differential) current. But it would not be zero. And that is the point. There can be unintended (although very small) common mode (by our definition) currents flowing in places we don’t expect.

So What’s The Problem?
The problem with common mode currents is we don’t know where they are flowing! And they may be flowing in very (relatively) large loop areas. If so, they may be radiating very significantly. Such a common mode signal, only a tiny fraction of the magnitude of a primary signal but radiating many times more “loudly”, can become a significant EMI problem!

Relationship To Conventional Definition
Figure 2 illustrates the conventional definition of common mode current (ic). It is usually shown as appearing on both the trace and ground, flowing towards the receiver.

Figure 2: Identification of Differential and Common Mode Current Components

First, there is no necessary reason that it flow toward the receiver; it could just as easily exist on the trace and plane flowing away from the receiver (though we might have trouble envisioning how such a signal might be generated.)

We suggested that common mode current is any current that flows in the circuit along a path other than the one we intended. ANY combination of signal and return current can be broken into differential and common mode components suggested in Figure 2 (assuming common mode currents exist at all.) For example, assume that the signal current on the trace is 10,000 ua (10 ma) and the return signal on the plane under the trace is only slightly smaller, say 9,950 ua. This, then, means that there is 50 ua flowing back to the driver along some other path. The differential and common mode components of Figure 2, therefore, under these assumptions, are Id = 9,975 ua and Ic = 25 ua.

What Do We Do About Common Mode?
Since common mode currents are unintended, it seems like they would be difficult to control. And indeed that can be the case. However, here are a few basic ground rules for controlling common mode problems:

Use good high-speed design techniques everywhere in your design.
In particular, maintain a solid, continuous reference plane for every trace.
Common mode problems are smaller for stripline traces contained between planes. If possible, route all critical traces in stripline environments.
Minimize (or eliminate) the presence of any stubs or extraneous trace lengths associated with any high-speed trace.
Try to eliminate any path for a signal to flow on other than the intended path(s).

Since, ultimately all signals flow from the power plane through a driver to a receiver to the ground plane and back to the power plane, minimize this path length. One way to do this is to use power/ground plane pairs in your board stackup. Then ensure there is good capacitive decoupling between these two power sources.

Differential Mode Radiation
Most of us have heard that the high-speed signal return path is on the plane directly underneath the trace.⁴ Many of us, however, are not aware of how important it is that this be the case. The importance relates to a concept called “loop area.”

Current flows in a loop. On a typical trace, the loop is defined by the length of the trace, the path through the receiving device, and the return path on the plane directly underneath the trace. Conceptually you can define the area within this loop. It is approximately equal to the length of the trace times the height of the trace above the plane. The importance of loop area is this:

In high-speed designs, EMI is directly related to loop area. If you want to minimize EMI, you must minimize loop area.

It’s as simple as that. Most of us are intuitively aware that traces, even microstrip traces, routed close to planes, generally perform well from an EMI standpoint. That’s because their loop areas are small. In the next few paragraphs we’ll look at illustrations where loop areas might get out of control, perhaps unexpectedly so.

Slots In Planes
Figure 3 shows a trace crossing a slot or discontinuity in the plane. What might cause a slot or discontinuity in a plane? Perhaps you (as a board designer) have finished the design and then your engineer comes to you with “one more little part” that needs to be added. Making provision for the routing of this new part may involve significantly shifting already routed nets. But, perhaps, you could just put a little slot in one of the planes, route the new trace(s) in that slot, and finish the board quickly. Or, perhaps the plane has been partitioned in some way, creating a discontinuity. Or perhaps there is a special component requirement nearby that results in a small discontinuity.

Figure 3: Routing a trace over a slot in a plane can cause a large loop area

No matter what the cause of this slot or discontinuity, if a high-speed trace is routed over it, the return signal will want to travel under that trace. When the return signal hits the discontinuity, it must travel around it and then come back to its position under the trace again. This trip around the slot or discontinuity creates a loop. Since EMI is related to loop area, we have now created a possible EMI problem where none previously existed.⁵ (Note that Figure 3 resembles what is commonly known as a “slot antenna!”)

Connectors
Figure 4 illustrates a case where two boards are connected through a connector. The signal between IC1 and IC2 travels through connector A. In one case, provision for the return (usually a ground pin) is provided at point A. In this case the loop area is probably small. But in the other case, provision for the return signal is provided at point B. This may be a different connector (a particularly reckless thing to do!), or perhaps a pin on the same connector significantly separated from the signal at Pin A. In either case the loop area could be large and EMI could become a problem.

Figure 4: Be careful when routing through connectors to minimize loop areas

Clearance Holes
Figure 5 illustrates a row of clearance holes for pins for perhaps a component or connector. In Figure 5 (a) and 5 (b), a signal trace connects to one pin and the return (ground) pin is on the back side. In 5 (a) the clearance holes are wide enough to remove all the copper from the plane. The return signal, traveling under the trace, must then travel around the copper void area to get to the ground pin. This creates a loop that might become an EMI problem.

Figures 5A, 5B, 5C: Provide clearance paths or pin assignments to minimize loop areas

A better solution is shown in 5 (b). The clearance holes are smaller, so that they do not remove all the copper from the plane in this area. Now there is a path for the return signal to travel between the pins to the return (ground) pin. This approach is marginally better than 5 (a) and will result in a smaller loop area. And this illustrates why it is usually preferable to provide a copper path on the planes through all areas like this.

But there is an even better solution 5 (c). If you have the flexibility to do so, it is best to assign pins so that there is always a ground (return) pin beside every signal pin. This provides the absolute minimum loop area for the signal and its return, and results in the best EMI performance.

Power Plane Returns
Now let’s look at an interesting complication to all this. The return signal will follow the path of least impedance. That is the point on the plane closest to the signal trace. What if that plane happens to be a power plane rather than a ground plane? How does the return signal get back from the power plane to the ground pin of the device?

First, DC voltage has no meaning to a high-speed return signal. The return signal can be just as happy on a power plane as it is on a ground plane. From an AC standpoint there is no difference between a power and a ground plane. The most obvious illustration of this point is all the bypass capacitors we have connecting the two planes together. From an AC standpoint the planes are shorted together all over the place!

So, what happens if the return is on a power plane? The exact answer may not be known. But the practical answer is that the return signal transitions from the power plane to the ground plane through a nearby bypass cap. And if we have very high frequency harmonics, the transition may be through the planar capacitance between the two planes themselves.

It may not be a satisfying answer that the signal passes through a nearby bypass cap. After all, that leaves the definition of the loop area somewhat up to chance. There are a few people, for example Howard Johnson and Henry Ott (two highly respected experts in the field) who have sometimes advocated the placement of bypass caps near connectors or devices simply to provide a path for the return current. The bypass capacitor would not be intended to provide a decoupling function at all. Its sole purpose would be to control the loop area for the return currents on the power plane and therefore control EMI.

Changing Trace Layers
Figure 6 illustrates another interesting case. Figure 6(a) shows a simple signal referenced to a plane. Figure 6(b) illustrates the trace transitioning to the other side of the same plane. In this case the return signal would simply transition to the other side of the same reference plane, and there should be no effect on loop area.

Figures 6A, 6B, 6C: Some engineers believe that routing traces on widely separated trace layers may increase loop areas

But what about the case shown in Figure 6(c)? Here the signal transitions to an entirely different trace layer and reference plane. A legitimate question is how does the return signal get back under the trace on the new signal layer?

Again, the not very satisfying answer is through a nearby bypass cap. And again, some people advocate placing a bypass cap near each via for the single purpose of providing a path for the return signal and reducing loop area. A few circuit design engineers even prohibit transitions of traces from one trace layer to a completely different one because of the potential for increased loop areas and EMI problems (though most engineers would call this an extreme position to take).

On the designs we do here at UltraCAD there are typically quite a few bypass capacitors. We generally take no particular special precautions when transitioning signals to different trace levels, nor do we pay particular attention to which plane (power or ground) the return signal is on. We are not aware of any design failures that can be traced to either of these practices.

Unrelated Planes
Many boards have separate, well defined, areas on them for different power systems. There may be both 3 Volt and 5 Volt power supplies, for example, or perhaps separate analog and digital power supplies (or even transmitter and receiver power supplies, etc.) Often, in such cases, we define planar areas for these supplies.

Figure 7 illustrates a situation where there are separate analog and digital power supplies and planes. Consider a trace that must be routed between the digital ICs 1 and 2. Ideally, the trace would be routed exclusively over the digital power plane. But what if we took the shorter path and routed it over the analog plane? The question is where is the return signal? And there are two possible answers to that, both of which are bad!

Figure 7: Routing a trace over an unrelated plane can cause several types of problems

One possible answer is that the return signal stays on the digital plane and flows around the analog plane. But this creates a wider loop area and therefore potential EMI problems. Another possibility is that the return signal somehow finds a path onto the analog plane and continues on under the trace. We may not have an EMI problem in this case, but what we do have now is a digital signal on the analog plane. This digital signal might interfere with other analog signals in the area and create a crosstalk or ground noise problem. After all, the whole reason we have separate power systems is to keep the analog and digital signals separated in the first place! Either possibility is bad! So the right answer is: don’t route traces over unrelated planes.

Other Techniques
There are other techniques for controlling EMI. One goes by the term “picket fence,” also known as a “Faraday shield.” A fence is created around the board by dropping closely spaced vias around the perimeter. Another technique makes prodigious use of copper foil around the enclosure! These techniques, of course, are designed to keep already generated EMI radiation from escaping. Unfortunately, they do nothing to protect the other circuits within the enclosure from being impacted by the EMI that has already been generated.

A better solution, I propose, is to prevent significant amounts of EMI from being generated in the first place, using the techniques described above. Then the problem of keeping the radiation within the enclosure goes away.

Douglas Brooks is president of UltraCAD Design, Inc. (www.ultracad.com), a printed circuit design service bureau in Bellevue, WA, that specializes in large, complex, high density, high speed designs, primarily for the video and data processing industries. Brooks is the author of Signal Integrity Issues and Printed Circuit Board Design (Prentice Hall, 2003), and can be reached at doug@ultracad.com.

Notes

Hartley, “Controlling Radiated EMI Through PCB Stackup,” Printed Circuit Design Magazine, July, 2000, p. 16.
It is sometimes disquieting that we usually spend an enormous amount of time and effort routing only 50% of the signals (the traces). We tend to ignore the other 50% (the returns). The return paths are equally as important as the traces and designers need to know where those return paths are!
I am indebted to several people who helped me clarify my views of common mode issues during a series of e-mail communications in early 2002. Among them are Eric Bogatin (Gigatest), Jim Knighten (Teradata Division, NCR), and Todd Hubing (Professor, University of Missouri, Rolla).
The reason for this relates to issues of mutual inductance and the fact that this is the lowest impedance path (the path with lowest overall inductance.)
For more reason why slots in planes are a bad idea, see Brooks, Douglas, “Slots in Planes, Don’t Use ‘Em,” available through the articles pages at www.ultracad.com.