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Maintaining good signal integrity while providing adequate electrostatic discharge (ESD) protection at a system level is increasingly challenging. Interface speeds for digital consumer electronics and personal computers are rapidly increasing. HDMI, DisplayPort, and eSATA are already running at multi-gigabit/sec data rates, and other ports such as USB are expected to continue the trend within the next year.

These higher speed circuits are usually implemented in the latest semiconductor manufacturing geometries, which are more vulnerable to ESD damage. Semiconductor devices are predicted to become increasingly prone to ESD damage as these geometries continue to shrink,¹ increasing the need for robust ESD protection external to the transmitter and receiver chips.

Integrated circuit manufacturers have continued to decrease the minimum dimensions of the transistors, interconnections, and the SiO₂ insulation layers in their devices. This results in smaller structures for higher speed devices which are more susceptible to electrical overstress (EOS) breakdown damage at lower energy levels. SiO₂ layers are more likely to rupture and metal traces are more likely to open or bridge during an ESD event.

High speed receivers and transmitters will usually include some on-chip ESD circuits to provide protection within a controlled manufacturing environment, but a typical real-world ESD event can deliver a peak current of over 30 Amps, and enough I²R heating to permanently destroy the relatively small input clamps in a deep sub-micron receiver or transmitter IC. Therefore, system designers must use external ESD protection devices to ensure adequate system reliability.

Unfortunately, ESD protection devices and associated design techniques that were successfully used for slower speed ports such as USB 2.0 (480 Mbps) are inadequate for these higher data rates. There are several challenges confronting a design engineer trying to provide excellent signal integrity with adequate ESD protection:

Retaining good signal integrity suggests minimizing shunt parasitics, such as stray capacitance;
As the capacitance of an ESD protection circuit goes down, the EOS shunt power capacity is reduced and the protection level tends to degrade. Lower capacitance usually means higher clamping voltages and higher residual current into the protected ASIC, both of which contribute to ESD damage;
At these high speeds, seemingly secondary issues such as capacitance matching, pinout and routing options become much more important than at lower data rates;
ESD product datasheets can sometimes list confusing or misleading information regarding key product parameters;
Pin-compatible parts can often vary widely from vendor to vendor, and in some cases lot to lot, which can lead to signal integrity problems in the field even if a system appears to work well in the lab.

Complicating these issues are other manufacturing constraints that are often placed on the design engineer. For example, consumer electronics manufacturers often use several PCB board vendors. The board vendors can have different board stack-up parameters such as dielectric thickness, which makes it difficult for engineers to do an impedance controlled layout that is portable from vendor to vendor.

While these challenges appear daunting, by carefully selecting ESD components and applying good design techniques, it is possible to provide excellent ESD protection while simultaneously maintaining excellent signal integrity at multi-gigabit data rates.

Capacitance Specifications
Most engineers understand that, as data rates increase, they need to select lower capacitance ESD devices to minimize signal attenuation (see Figure 1). Generally, for these data rates, it is recommended that capacitance be kept below 1.5 pF², although in practice it is better to choose even lower capacitance devices, provided they can achieve sufficient levels of protection.

Figure 1: Decreasing capacitance improves signal attenuation at higher frequencies

One common problem in identifying device capacitance is that it is often inadequately specified or in some cases specified in misleading ways. The engineer should look for two key parameters in a datasheet:

Typical junction capacitance (I/O to Ground)
Maximum junction capacitance (I/O to Ground)

Most vendors list their typical capacitance, but many do not list their maximum capacitance. If this is not specified, it is possible that lot-to-lot production variations from the ESD vendor may cause signal integrity problems in the end systems.

Unfortunately, this is not the only datasheet comparison problem. Some ESD component vendors highlight their ESD devices based on I/O to I/O capacitance rather than I/O to Ground capacitance. It is important to identify the correct, consistent parameter, as well as the related effects. The actual junction capacitance (I/O to Ground) can be more than 100% higher than the capacitance between two I/O pins, causing impedance mismatches and requiring layout changes to compensate for the higher capacitance. I/O to I/O capacitance can be related to cutoff frequency, or crosstalk, depending on which pins are referenced.

Discrete diodes are another source of problems in this regard. Single channel diode solutions such as BAV99s have historically been used by engineers to protect moderate speed ports such as VGA and full speed (12Mbit/s) USB. These signal diodes are not as reliable for ESD protection as ESD-rated diode arrays, but are popular because they are inexpensive and available from numerous vendors. They consist of two steering diodes on two independent dice, which are typically connected between power and ground, with the signal line connected in the center via high inductance bonding wires.

BAV99s all specify their capacitance as a maximum of 1.5 pF; however, this is the capacitance of each individual diode, so the actual junction capacitance can be twice that, or 3.0 pF. In practice, the capacitance on these parts can vary up to 200% from vendor to vendor and lot-to-lot, creating unforeseen impedance mismatches, signal skew, and EMI problems. This type of issue can often go unnoticed in the test lab, only to be discovered when systems are shipping and quality issues are being reported by end customers.

Figure 2: Single Channel BAV99 diode structure

Finally, as mentioned, lower capacitance often results in higher clamping voltages and residual current reaching the protected circuits. With high speed circuits migrating to smaller geometries that are more sensitive to ESD damage, solutions that previously worked to protect a system may no longer work in the next generation design. This makes it critical for engineers to carefully balance the tradeoff of capacitance vs. ESD protection capability.

While there are several general rules that can be applied, such as using devices with lower dynamic resistance and using semiconductor-based ESD devices rather than poorly performing varistors and polymer solutions³, it is critical that the system undergo system level ESD testing per the IEC61000-4-2 industry standard specification to truly determine whether the ESD protection device is sufficient.

Matched Capacitance
Many design engineers are familiar with basic principles of high speed layout, such as avoiding vias, and keeping trace lengths matched. Vias and stubs cause impedance mismatches and reflections, while unmatched trace lengths contribute to signal skew and EMI problems. Just as importantly, it is critical to have matched capacitance between ESD protection devices to avoid these problems.

Most high speed I/O ports, such as HDMI, DisplayPort, and eSATA, use differential signaling which consist of pairs of signal lines that swing opposite to each other around a center voltage. To maintain good signal integrity, they require very tight tolerances on intrapair skew. For example, DisplayPort requires a maximum of 20 pS of skew at the transmit pins of the system.

Even small capacitance mismatches can cause large skew variations. For example, a seemingly small difference of 0.2 pF between two ESD devices can cause skew variations greater than 40 ps at critical points, reducing the margin in eye diagram mask tests.

With discrete protection devices, this can be difficult to avoid; as shown earlier, BAV99s can range from < 1.0 pF to 3.0 pF, or 10 times the mismatch depicted in the example above. The best way to control capacitance matching is to use an integrated diode array. By manufacturing all of the diodes on a single die, typical diode arrays from leading ESD vendors can provide capacitance matching at < 0.05 pF, minimizing signal skew and EMI problems. With a multi-channel diode array, the system engineer can ensure channel-to-channel matching by design, and avoid large field variation when a new discrete diode vendor or wafer lot is merged into production lines later on.

Figure 3: Small 0.2 pF capacitance difference between lines can introduce significant skew

Packaging and Layout Issues
Selecting an ESD protection device with low capacitance and matched capacitance is not in itself sufficient to assure good signal integrity. Choice of package can be just as important. Packaging of the ESD device can have several effects on signal integrity. The most obvious one is how easy or difficult it is to route a signal to a given package. Routing is particularly important with differential signals for several reasons:

Difficult routing can force the designer to use vias, affecting impedance;
Poor package choice can force the designer to route signals using unequal length, adding signal skew;
Changes to the distance between differential pairs can make it difficult to achieve matched impedance.

The best way to route high speed signals is to use routing that goes straight through or straight under the ESD device, minimizing any discontinuities caused by routing. Figures 4 and 5 illustrate the differences between using discrete single channel devices vs. an optimized straight-through routing.

Figure 4: HDMI TMDS routing using 8 single channel devices in SOT-23 packages

Figure 5: HDMI full port routing using single 12-channel CM2021-02 device

In Figure 4, the HDMI system designer must route around and under packages, creating unequal trace lengths and introducing additional parasitic capacitance along the trace due to routing under multiple packages. The solution in Figure 5, which is now available from several vendors, eliminates these problems by matching the signal and ground return pins directly to the pins on the connector, using the same spacing and pin assignments.

When considering the multi-channel device, consider the effective pin pitch of the entire solution. An MSOP device may have 0.5mm pitch pins, but when total body width and power/ground pins are considered, the effective pin pitch of two packages grows to slightly larger than 0.5mm, and some fanout of the pairs must be done, using additional board space. Very often, a “large” 8-channel package takes up less board space than two 4-channel or four 2-channel devices.

Summarizing capacitance issues:

Lowering capacitance of the ESD circuit is important for signal integrity, but care should be taken to ensure that the device can still provide adequate ESD protection;
Matching capacitance can be as critical as having low capacitance, since mismatched capacitance can cause signal skew and EMI problems;
When possible, choose a semiconductor-based ESD device (best performance) in a package that allows simple straight-through routing, minimizing trace length mismatches, reflections, and skew.

Impedance Matching and Other Design Compensation Issues
Regardless of how low the capacitance of an ESD device is, there is going to be some level of signal distortion introduced by any device added to a signal line. At GHz transmission frequencies, even small amounts of capacitance can be a problem.

A simple method for understanding the signal integrity on a transmission line is to look at the impedance along that line. The goal of a designer is to provide matched differential impedance along the line to minimize reflections and signal attenuation. A common method for determining the characteristic differential impedance of a transmission line is called time domain reflectometry (TDR). A TDR plot shows the differential impedance of the transmission line along the signal traces. As capacitance is added to a line (such as when adding an ESD diode to an HDMI signal path), the characteristic impedance of that line will drop.

Table 1 shows the relative effects of a very small change of capacitance relative to the change in differential impedance. These results were obtained by using two ESD devices in identical footprints on the same board. The board was designed with 100 ohm differential traces, and the TDR was measured with a rise time of 200 ps. No compensation was done to offset the effects of the diode capacitance on these boards. The results show that even a small difference in capacitance can have a dramatic impact on the impedance of the transmission line. In this case, even the lower capacitance device caused a 6 ohm drop in impedance, and increasing the capacitance by a mere 0.22 pF caused an additional 4 Ohm drop.

	Capacitance	Minimum Impedance	Discontinuity Deviance
ESD Clamp A	0.53pF	94 Ohms	-6 Ohms
ESD Clamp B	0.75pF	90 Ohms	-10 Ohms

Table 1: Comparing two capacitance levels on 100 ohm uncompensated differential traces

While both of these designs are well within the compliance limits for specifications such as HDMI 1.3 and DisplayPort 1.1a, they illustrate how even small variations in capacitance can dramatically impact the transmission line impedance and thus the signal integrity. As an additional consideration, not only do system designers need to compensate for the parasitic capacitance of the ESD device, but they also need to take into account part to part variations, and even board to board variations. Therefore, it is important to minimize impedance mismatches caused by the design itself.

Luckily, there are several methods for reducing the effects of capacitance on the characteristic differential impedance of a signal line. These controlled impedance design techniques are well-known to designers of communications equipment, which has been operating in multi-gigabit data rates for years. In contrast, most PC and digital consumer electronics designers have only faced these design challenges recently and may not be familiar with these techniques. Common design practices include:

Reducing board-level capacitance in the region of the ESD device;
Increasing trace inductance in the region of the device;
Adding inductance, such as a choke, to the line near the ESD device.

All of these techniques have advantages as well as limitations. The characteristic impedance at any point along the transmission line is a function of the square root of the unit characteristic inductance divided by the unit characteristic capacitance (see Equation 1). In other words, increasing capacitance causes the impedance to drop, while increasing the inductance causes the impedance to increase. Therefore, to offset the capacitance of an ESD device, the designer needs to reduce capacitance elsewhere in the vicinity of the ESD device or increase the inductance in that area.

Equation 1

Reducing Board Level Capacitance
This can be done by increasing the dielectric spacing to the ground plane under the trace, either by ordering a different PCB composition from the vendor, or by omitting an intermediate layer, i.e. Layer 3 GND + Layer 1 Signal, instead of L2+L1. Depending on the PCB board stackup, this can reduce the magnitude of discontinuities due to pad footprints (Co becomes smaller per unit area), but won’t completely offset the capacitance of the ESD device.

Increasing Trace Inductance
This is often called trace necking and can be very effective when only small amounts of compensation are required.  Reducing the width of the trace in the vicinity of the ESD device will increase the inductance, offsetting some of the capacitance of the ESD device. Like the previous technique, this also faces PCB limitations. For example, on thin dielectric boards, if the capacitance of the ESD device is too high, it can be difficult to achieve matched impedance by simply reducing the trace impedance, as this may require traces that are too thin to be manufactured reliably.

Adding Inductance Such as a Common Mode Filter (CMF)
Common mode filters are typically thought of as EMI suppression devices, but they can be used effectively to compensate for ESD parasitic capacitance as well as to compensate for some signal skew caused by mismatched devices between two lines. However, they also require valuable PCB board space, and are usually more expensive than the ESD devices themselves. In cost-conscious consumer electronics and computing markets, adding a CMF is typically only done as a last resort if the other techniques do not work because CMFs naturally add their own distortion and signal attenuation parasitics as well.

To deal with these problems for the designer, a new class of components are coming to market which do not require impedance matching while still providing excellent ESD protection. Rather than focusing solely on lowering capacitance, these devices incorporate additional inductance inside of the ESD package to offset the parasitic capacitance of the ESD diode.

To illustrate, first consider the traditional ESD layout depicted in Figure 6. The traces are routed directly under the package to maintain trace length matching and minimize turns. On each trace, one pin is connected to the ESD device, while the other pin is not connected. The impedance in the area of the diode is affected by the capacitance of the diode itself, the capacitance of both the ESD pin and the NC pin, and finally by the trace going underneath the package.

Figure 6: Traditional routing for 2-channel ESD device (ground connection not shown)

Figure 7: Routing using impedance matched ESD devices (ground connection not shown)

In contrast, this new approach removes the trace from under the package by routing up and through the package. As seen in Figure 7, this eliminates the parasitics of the trace under the package, and allows the inclusion of inductors in series with the diodes to offset their capacitance and achieve matched impedance.

The primary benefit of this approach is that it removes all need of the system designer to perform controlled impedance layouts that require custom modifications based on the board and ESD device parasitics. Instead, the designer can simply specify in their design that traces should be laid out for
100 ohms in the portions where there is no ESD device, and the device is designed so that it will meet signal integrity requirements without the need for any external compensation. This allows the same board to be manufactured at several PCB vendors without changing the layout, reducing design complexity, as well as development and bill of material costs.

A side benefit of this approach is that it also provides improved ESD protection. To see why, it is useful to compare simplified circuit diagrams for the traditional ESD approach vs. the route-through approach.

The internal circuit of a traditional ESD approach can be represented as shown in Figure 8.

Figure 8: Simplified circuit for traditional ESD protection solution

In this figure, the ESD device hangs off of the signal line. The parasitic capacitance of the ESD device creates the unwanted impedance drop in the line, while the bond wire inductance to the ESD circuit acts to slow down the ESD response time.

Figure 9, in contrast, shows the ESD device in the “signal through” configuration, where L1 and L2 are integrated into the package to create a matched impedance with the outside line. As can be seen, the L2 inductor acts to slow down the rise time of the ESD pulse seen at the ASIC , resulting in lower peak voltages and currents than would be seen using a standard ESD diode.

Figure 9: Simplified circuit for “route through” ESD device

Lab results indicate that this approach results in a 40% reduction in peak voltage seen at the ASIC during an ESD strike, as well as a 15-40% reduction in peak residual current seen at the ASIC.⁴

Summary
Higher speed circuits are increasingly prone to ESD damage as they migrate to smaller geometry silicon processes. Maintaining excellent signal integrity while providing adequate protection can be challenging, but there are several techniques available that can help the designer meet both goals:

Choose low capacitance solutions, but make sure to compare ESD performance and use the I/O to ground junction capacitance;
Choose integrated diode arrays rather than discretes to maximize capacitance matching and simplify layout;
Take care to match impedance when laying out ESD components, taking into account all PCB board stack-up information;
When possible, choose impedance matched circuits that integrate inductance with capacitance to eliminate external impedance matching design challenges.

With these techniques, it is indeed possible to achieve excellent signal integrity with excellent ESD protection. n

Jeffrey Dunnihoo is the senior systems engineer for PC and Consumer applications at California Micro Devices and can be reached at jeffd@cmd.com.

Joe Salvador is the company’s Director of Marketing for Consumer and Computer products, and can be reached at joes@cmd.com.

References

“Electrostatic Discharge Technology Roadmap”; ESD Association; March 4, 2005
“VESA DisplayPort Standard”; Version 1, Revision 1a, VESA, January 11, 2008
“Evaluating ESD Protection Circuits and Test Methods”, Joe Salvador, Conformity Volume 12, Issue 8, August 2007
Based on California Micro Devices’ test results comparing CM1233-08DE Picoguard XP vs. industry leading ESD TVS diode array.